1. Technical Field
This disclosure relates to computer systems, and more particularly to prefetching memory contents in a cache subsystem.
2. Description of the Related Art
Processors in computer systems rely on cache memories to support desired performance levels. With increasing demands for higher performance, a corresponding increase in the number and capacity of cache memories in a processor has followed. Many processors include multiple levels of cache, including a level one (L1) cache and a level two (L2) cache, with many processor also including a level three (L3). The L1 cache may be the closets to the execution unit(s) of a processor, and in some cases may be divided into separate instruction and data caches. The L2 cache may be the next closest after the L1 cache, with the L3 cache further from the execution unit(s) than the L2 cache. The L2 and L3 caches in many processors are unified caches, storing both instructions and data. At each succeeding level, the caches may become larger. Thus, an L2 cache may be larger than an L1 cache, while an L3 cache may be larger than an L2 cache.
One method of loading a cache memory is in response to a cache miss, i.e. when requested information is not found in the cache. However, cache misses incur a performance penalty which can be significant. Accordingly, many processors perform prefetching to load caches. Prefetching involves the speculative loading of information into the cache with the expectation that the prefetched information is likely to be used. Various types of prefetching may be performed. One type of prefetching is known as stride prefetching, wherein data is loaded from fixed address intervals. Another type of prefetching is known as next line prefetching, wherein an adjacent second line of data is automatically loaded into the cache responsive to the loading of a first line of data.